Magmio

FPGA-based system
for ultra-low
latency trading

Working with the Magmio trading platform is convenient, flexible, and doesn’t require any expertise in FPGA technology. It is very much like a Software Development Kit (SDK), only with your strategy running on the FPGA card instead of CPU.

Trading platform overview

Features

Feed handlers are easily portable to new markets and protocols, including FIX

The latency-critical parts of your trading strategy run purely on FPGA and independently of software

Order Book supporting thousands of symbols and both MBO and MBP feeds

C++ API for communication with the FPGA card

Order Entry and TCP offload engines with feedback to the strategy

The trading strategy implemented in C++ (you load your trading strategies written in C++ into the FPGA)

Success stories

What Magmio Actually Is?

Working with Magmio

Setting up your strategy for FPGA

You create your strategy code in the C++ language and insert it into our template. The input interface of the strategy template consists of the current state of the book, decoded market data, and custom parameters from software. The output interface abstracts from the exchange-specific protocols and provides unified access.

Compiling your strategy code

To translate your strategy into FPGA representation you run our tool, which internally uses an HLS compiler. The tool runs on your server, meaning the strategy code never leaves your hands. Moreover, FPGA is programmable, so you can independently & continually adjust your trading strategy.

Using your software application in C++

All the configuration and communication with the FPGA card is done via Magmio C++ API, abstracting you from low-level hardware. Your software is informed about everything that’s happening in the FPGA, enabling you to make quick adjustments to your strategy.

Interested in Magmio? Schedule meeting

What do you receive?

Trading algorithms

You will get an interface for creating trading algorithms for FPGA in a high-level programming language.

Optimized IP Cores

The Tick-to-trade pipeline in the FPGA is heavily optimized and handles only the latency-critical parts. The rest is kept in software to achieve the best performance.